1. Field of the Invention
The present invention relates to nonvolatile memory devices and methods for manufacturing such devices.
2. Description of Related Art
Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Conventional SONOS devices use ultra-thin bottom oxide, e.g. less than 3 nanometers, and a bias arrangement that causes direct tunneling for channel erase. Although the erase speed is fast using this technique, the charge retention is poor due to the charge leakage through ultra-thin bottom oxide.
NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell.
In addition, charge trapping memory devices capture electrons in a charge trapping layer in both shallow and deep energy levels. Electrons trapped in shallow levels tend to de-trap faster than those electrons in deeper energy level traps. The shallow level electrons are a significant source of charge retention problems. In order to keep good charge retention, deeply trapped electrons are preferred.
For commercial products it is desirable for such devices to hold data for at least ten years without loss. However, leakage of trapped charge, from shallower and deeper traps both, occurs in such devices due to defects in the materials which accumulate over long use, or which are inherent in the structures. One known class of defects in charge trapping structures is hydrogen inclusions in dielectric layers and structures. The hydrogen inclusion occupies a weak bond in a silicon material, such as silicon dioxide and silicon nitride, and can dissociate from the lattice structure of the dielectric and become a charge carrier, which then can contribute to charge loss. FIG. 1 provides a graphical representation of a typical memory cell based on charge trapping structures. The memory cell comprises a terminal 10 acting as a source, a terminal 11 acting as a drain and a channel region 12 in the substrate. A bottom dielectric layer 13 overlies the channel region 12 and portions of the source and drain terminals 10, 11. A charge trapping layer 14 overlies the bottom dielectric and a top dielectric 15 overlies the charge trapping layer 14. A gate electrode comprising a polysilicon layer 16 and a silicide layer 17 lie over the top dielectric layer 15. A small region of the bottom dielectric layer 13, charge trapping layer 14 and top dielectric layer are expanded heuristically in the region 20 on the drawing. Silicon atoms are shown schematically with four lines representing the valence electrons normally available for bonding, including the three pronged lines coupled on one side of the Si symbols, with one prong on the other side. Most of the bonding sites are occupied in the top and bottom dielectrics by oxygen. However, some hydrogen atoms attach to dangling bonding sites in the lattice structure, becoming trapped hydrogen inclusions in the dielectric, illustrated by the H in a circle. In the charge trapping layer 14, most of the bonding sites are occupied by nitrogen, with some hydrogen inclusions.
A number of investigators have looked at replacing hydrogen inclusions with deuterium isotopes of hydrogen, which form stronger bonds with silicon and do not dissociate and become charge carriers as easily. See for example U.S. Pat. No. 6,670,241 entitled SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS, by Kamal et al. Kamal et al. suggests that the top and bottom oxides in an ONO charge trapping layer, as well as overlying structures such as polysilicon wordlines, and the silicon nitride charge trap, all of which contain silicon, can be “deuterated” to improve charge retention characteristics of the memory cell. (See, column 5, lines 56–61, and column 4, lines 43–52.) However, improved processes and structures are desirable which can be applied to very small devices, and achieve long retention times.